1. Field of the Invention
The present invention relates to a test circuit such as a built-in self test (BIST) circuit and method for testing a high-speed semiconductor memory or other circuits to be tested, and a semiconductor integrated circuit device including a test circuit and a logic circuit (a CPU, for instance) disposed in the same semiconductor substrate.
2. Description of the Related Art
A variety of test circuits for testing the performance of a semiconductor integrated circuit such as a semiconductor memory have been proposed. For instance, Japanese Patent Application Kokai (Laid-Open) Publication No. 2004-93421 discloses a BIST circuit for testing a synchronous dynamic random access memory (SDRAM). The BIST circuit receives a test input pattern (a test clock tck, a test mode signal tms, and a test data input signal tdi) which is a standard serial interface signal conforming to the JTAG standard, for instance, generates a test pattern based on a test mode selection signal ctrl determined in accordance with the test mode signal tms and the test data input signal tdi, and tests an SDRAM as a circuit to be tested using the generated test pattern.
However, the conventional BIST circuit described above is configured to test the SDRAM while a test input pattern (a test clock tck, a test mode signal tms, and a test data input signal tdi) is being supplied. Therefore, if the input test pattern is interrupted or modified while the SDRAM is being tested, the test may be aborted or may be disabled.